Commit Graph
2 Commits
Author SHA1 Message Date
Claude b6529719dd refactor(sheets, settings): drop the last sheet-ring remnants and dead settings
The far sheet ring was already gone from the runtime; this removes what
was left of it:
- UVoxelSettings::bFarSheetRing / FarSheetSpanLevels, the
  voxel.TestFarSheetRing switch, and their log/trace/dump fields.
- The sheet branch of VoxelClipmapDesiredTiles (FParameters sheet fields,
  OuterShell sheet level, sheet ring emission). Output for the runtime
  configuration (sheet off) is unchanged: same rings, same alignment.
- Tests: VerticalStrateReach now asserts the sheet-free selector (its
  expected counts were stale since the aligned-ring change 85a803b:
  LOD0 343 -> 512); ClipmapNoOverlap drops the sheet sweep cases and the
  frozen 7486c29 oracle's sheet branch. New expected values were computed
  with a Python port of the selector that reproduces the test's existing
  635/594487 and 508/74295 measurements exactly; all 5,145 sweep cases
  pass (no overlap, full coverage).
- Tools/VoxelForgeTest.ps1 no longer passes voxel.TestFarSheetRing or
  reports far_sheet_ring. The sheet_tile dump field is kept (the parity
  compare reads it).

Also removes settings nothing reads: CeilingViewMultiplier,
CeilingBandChunks (pre-clipmap ceiling band) and DensityVolumeMaxTasks
(the volume fill runs on its own thread). Saved assets that still carry
these values load normally; the values are ignored.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01URDGLsu7c4nunqNFPJEFPU
2026-09-28 14:53:25 +00:00
Fr0zkaandClaude Opus 5.5 85a803b873 wip(streaming): LOD rings tile exactly once, cache race, reconcile 104x -- gate stress FAILS 3/4
- Clipmap: finer rings snap to child-pair boundaries, so no two desired tiles of different
  levels overlap. Owner config 635 overlapping pairs -> 0; LOD0 ring 343 -> 512 tiles.
  New test sweeps 6,174 cases; fails on 7486c29 as intended, passes here.
- Shared room-graph cache: Entry->Cache read/written only under the mutex (race fix).
- ReconcileReadyTransitionVisibility indexed: moving p95 32.0 ms -> 0.31 ms.
- Block-vs-scalar density equivalence test: 5.1M samples bit-identical; catches an injected
  optimistic EffectOverBox (5,612 mismatches).

UNVALIDATED for merge: collision-gate stress passed 1 of 4 runs on this code (fails at 4.56 m,
support collision unready at start); it passed on 7486c29. No control run yet.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MmSoF64BbRFmk9C3p1VsBJ
2026-09-25 02:47:54 +02:00