Fr0zkaandClaude Opus 5.5 08cc3bd89b core: per-tile passage route IDs and empty-feature early outs (L136, output = v236) ...

Passage visits -78..-89% near-ready; composer worker time back to baseline on Tunnel Network; v239 is 2-4% faster
than v236 in 7/8 cells but still +4.3..+13.3% near-ready vs assembler/world. Surface World composer time equals
baseline yet near-ready is +4-6%: unexplained. 16/16 seeds, fast tier, Clang/GCC green.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_016dhxM43dnWvUu2B5Ph1iG1

2026-11-01 01:15:09 +01:00

..

DesignD2

design: world assembler -- Luna D2 + Claude response

2026-10-08 23:24:25 +02:00

OwnerShapeWorld

wip(assembler): round S8 -- region rebuilds no longer stall admission; result backlog capped

2026-10-19 09:43:03 +02:00

VoxelSpeedRound

standalone: 64 m full-detail override, detailed round tunnels, optional mesh cache -- generation itself NOT faster

2026-10-03 08:59:46 +02:00

WorldAssemblerM1

wip(assembler): M1 round 4 -- cap rebuilt (no hiding), sub-voxel audit, routes + mesh-free queries

2026-10-09 14:23:38 +02:00

WorldAssemblerM2

wip(assembler): M2 round 4 -- WorldAssemblerHybridV2: exact contacts, tagged tiles 1.18-1.27x MC

2026-10-10 10:41:43 +02:00

WorldAssemblerM3

core: per-tile passage route IDs and empty-feature early outs (L136, output = v236)

2026-11-01 01:15:09 +01:00