Fr0zkaandClaude Opus 5.5 6e52fb48b2 research: L118 passage-tile designs (hash-exact, no readiness gain; kept as patch) ...

Tagged the passage bucket: per-tile prepareSweptTubeBase dominates (0.47-0.92 s summed per view),
smooth-min second. Segment lower-bound pruning (-17% pairs) and deferred fallback floor work stayed
hash-exact but moved near-ready <3%. Still +17..+26% vs L109.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_016dhxM43dnWvUu2B5Ph1iG1

2026-10-30 04:39:40 +01:00

..

DesignD2

design: world assembler -- Luna D2 + Claude response

2026-10-08 23:24:25 +02:00

OwnerShapeWorld

wip(assembler): round S8 -- region rebuilds no longer stall admission; result backlog capped

2026-10-19 09:43:03 +02:00

VoxelSpeedRound

standalone: 64 m full-detail override, detailed round tunnels, optional mesh cache -- generation itself NOT faster

2026-10-03 08:59:46 +02:00

WorldAssemblerM1

wip(assembler): M1 round 4 -- cap rebuilt (no hiding), sub-voxel audit, routes + mesh-free queries

2026-10-09 14:23:38 +02:00

WorldAssemblerM2

wip(assembler): M2 round 4 -- WorldAssemblerHybridV2: exact contacts, tagged tiles 1.18-1.27x MC

2026-10-10 10:41:43 +02:00

WorldAssemblerM3

research: L118 passage-tile designs (hash-exact, no readiness gain; kept as patch)

2026-10-30 04:39:40 +01:00