Fr0zkaandClaude Opus 5.5 b5ed321b9e wip(L16, side branch): disk terrain cache design + headless Linux prototype ...

Exact lossless zlib tile records (keyed on world/season/recipe/plan/evaluator/options/tile),
pristine cache plus ordered edits, server never trusts client caches, corruption/stale rejection,
atomic writes, 2 GB cap. Loaded tiles match regenerated hashes (L1 view, 24 m crossing).
NOT for assembler/world yet: the shared StreamBenchmarkPipeline.h includes Linux-only headers
(unistd/fcntl/zlib), which would break the Windows viewer build.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01CSFYgsdW8ejZSyiMf4qRSX

2026-10-20 04:19:56 +02:00

..

DesignD2

design: world assembler -- Luna D2 + Claude response

2026-10-08 23:24:25 +02:00

OwnerShapeWorld

wip(assembler): round S8 -- region rebuilds no longer stall admission; result backlog capped

2026-10-19 09:43:03 +02:00

VoxelSpeedRound

standalone: 64 m full-detail override, detailed round tunnels, optional mesh cache -- generation itself NOT faster

2026-10-03 08:59:46 +02:00

WorldAssemblerM1

wip(assembler): M1 round 4 -- cap rebuilt (no hiding), sub-voxel audit, routes + mesh-free queries

2026-10-09 14:23:38 +02:00

WorldAssemblerM2

wip(assembler): M2 round 4 -- WorldAssemblerHybridV2: exact contacts, tagged tiles 1.18-1.27x MC

2026-10-10 10:41:43 +02:00

WorldAssemblerM3

wip(L16, side branch): disk terrain cache design + headless Linux prototype

2026-10-20 04:19:56 +02:00