Fr0zkaandClaude Opus 5.5 87b0e5d8cd wip(assembler): round S13 -- tile cost counted per LOD (diagnostics only, no output change) ...

Exclusive per-stage tile timers and probes. Findings: LOD0 is MC-exclusive
(10.4 of 14 ms p95, 243 ns/sample); LOD4's 3x cost is column-cache misses
(8,224 vs ~1,600-1,900 at LOD3/5), cap refine secondary; per-tile feature lists
cost ~0.001 ms; cross-worker column repeats common (277k at LOD0). Global octave
drop and stride-2 interpolation probes fail the 2 cm gate. Worker cap 1 kept
(cap 0 worse 40 m/s tick tail). Report: Standalone/Research/WorldAssemblerM3/Round17.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MmSoF64BbRFmk9C3p1VsBJ

2026-10-19 15:40:25 +02:00

..

REPORT.md

wip(assembler): round S13 -- tile cost counted per LOD (diagnostics only, no output change)

2026-10-19 15:40:25 +02:00