VoxelForge/Standalone/Research/WorldAssemblerM3/Linux175/REPORT.md

# L175 — passage tile seams

## Cause

Tile B took the packed base-only X8 path because its fast predicate checked only
that edits were empty and the requested X/Y/Z samples were inside the cached
base-field bounds. It did not ask whether any lane was inside a passage feature
bound. The measured trace for tile `(0,1,-32)`, at the shared `z=-2048` plane,
has `fast=1`, all base-bound checks true, `route_candidates=2`, and
`feature_aabb=1`; it then reports `path=packed_x8_base_only` with `-4.125`, while
the composed scalar result is `+0.781364381`. The corresponding seam sample is
`(16.5, 28.5, -512 m)`, a `4.90636438` density delta. See
`Saved/Linux/l175/dispatch-trace/seed0-seam-only-trace2.log`.

The bound and edge hypotheses did not fit the trace. Route influence reach is
`0.75 m shell + 0.21 m wall relief + 0.50/6 m corner support + 0.01 m guard =
1.053333… m`; route boxes add the maximum tube radius and a 0.01-core-voxel
rounding margin. Landing chamber bounds include their full radius, floor
gradient, clear height, and reach. Point and tile-box comparisons are inclusive.
The tile query covers `origin..origin+extent` plus the one-step normal stencil,
also inclusive. Those bounds are in core-voxel/subvoxel units. No unit, LOD-step,
or shared-edge omission was found.

A second composition-order issue was measured: a tile can list a passage because
another segment overlaps it, then compose that passage's landing chamber before
checking whether the current sample lies in the route feature AABB. Different
candidate lists could therefore alter samples outside the route segment. This
was fixed with the dispatch issue.

The reach ablation (`reach-proof-seed0-final.log`) covered 512 tiles and
21,952,000 samples at each of 1.5, 2.0, 2.5, and 4.0 m. All four comparisons
passed, with 150,096 shared crossings and no changed samples, crossings, mesh
edges, or normals. This supports the source-derived bound; the direct dispatch
trace identifies the root cause.

## Fix

In the shared layer, X8 lanes inside a passage route AABB now use the fully
composed scalar path. Only contiguous runs proven outside all route AABBs are
delegated to packed X8. The packed source also fails closed to scalar when it
has resolved passages but no tile-query proof. Before passage composition, a
sample outside a listed passage's route AABB now skips that passage entirely,
including its landing chamber.

The L175 seed-0 counter measured 23 route-bound LOD1 dispatch scopes. The old
predicate would admit all 23 to packed X8. With the fix, 22 scopes retain at
least one proven-unaffected packed run; 16 scopes send affected lanes through
scalar composition, and one scope has no unaffected packed run. These are
scopes where the X8 dispatcher ran, not a census of every generated tile.

`WorldAssemblyEvaluatorVersion` is now 241. Clang and GCC builds both use source
stamp `4d2512ec24add53e06effe1bd82dab5efafa9c450c815d3fc933c58e43327342`.
Across 18 canonical runs, all compiler/worker hashes matched for owner4
surface-world, owner2 surface-world, and owner2 floating-islands at W1/W8/W12.
Each owner2 v241 baseline changes 3 canonical rows from v240; both new baseline
files and the `verify.py` references are updated.

## 16-seed seam results

The Tunnel Network and Vertical Shafts route audits ran for seeds 0–15. Across
all seeds: **99,269 adjacent pairs, 121,604,525 shared samples, and 0 natural
mismatches**. The injected control still works: it creates one marked mismatch
and reports `injected=DETECTED` (`injected-seed0-final.log`).

| Seed | Pairs | Shared samples | Mismatches | Seam coverage | TN route | VS route |
|---:|---:|---:|---:|:---:|:---:|:---:|
| 0 | 7,579 | 9,284,275 | 0 | PASS | PASS | PASS |
| 1 | 6,417 | 7,860,825 | 0 | PASS | PASS | PASS |
| 2 | 5,273 | 6,459,425 | 0 | Coverage only | FAIL | PASS |
| 3 | 4,612 | 5,649,700 | 0 | PASS | PASS | PASS |
| 4 | 5,092 | 6,237,700 | 0 | PASS | PASS | PASS |
| 5 | 5,501 | 6,738,725 | 0 | Coverage only | PASS | PASS |
| 6 | 7,236 | 8,864,100 | 0 | Coverage only | FAIL | PASS |
| 7 | 6,912 | 8,467,200 | 0 | PASS | PASS | PASS |
| 8 | 6,537 | 8,007,825 | 0 | PASS | PASS | PASS |
| 9 | 7,080 | 8,673,000 | 0 | PASS | PASS | PASS |
| 10 | 7,715 | 9,450,875 | 0 | PASS | PASS | PASS |
| 11 | 5,933 | 7,267,925 | 0 | PASS | PASS | PASS |
| 12 | 6,703 | 8,211,175 | 0 | Coverage only | PASS | PASS |
| 13 | 5,916 | 7,247,100 | 0 | PASS | FAIL | PASS |
| 14 | 4,720 | 5,782,000 | 0 | PASS | PASS | PASS |
| 15 | 6,043 | 7,402,675 | 0 | Coverage only | PASS | PASS |

The strict seam audit status is PASS for 11/16 seeds. Seeds 2, 5, 6, 12, and
15 fail only its per-disc coverage requirement: one disc has LOD0 samples but
zero LOD1 samples on shared faces. All six end runs have both LODs covered in
each seed; there are no exempt pairs. The measured result is that no LOD1
shared-face sample was tagged to those discs. The likely explanation is that
the discs do not cross a sampled LOD1 seam; that is an inference from the
coverage output. This is missing feature-on-seam coverage, not a measured
density mismatch. The audit was left strict. Tunnel Network route gates pass
13/16 and Vertical Shafts pass 16/16. Overall sweep rows remain failed by the
existing passage, naturalness, self-overlap, route, and count gates; no step-2,
step-3, or LayerPlanner work was changed.

## Mainline `assembler/world` verdict

**Yes, the mainline at `e3359d2` has the same unsafe dispatch structure.** Its
packed X8 predicate checks cached base bounds without checking passage
influence, and passage composition happens later. The untouched setup stopped
before the seam audit (`grade_rejected=3460`, `sweepable_candidates=0`). In the
throwaway `/tmp/l175-mainline` build only, a scratch environment gate selected
the best of 148 candidates while explicitly skipping grade, capsule, and
support checks. With that setup bypass, the bounded LOD0 seam audit examined
129 candidate tile pairs, compared 49 shared pairs/60,025 samples, and found
0 mismatches. This limited sample does not show the mainline is safe; it did not
exercise the original 16-seed sweep.

The minimal mainline fix to schedule is the same shared-layer change: test each
X8 lane against passage bounds before delegating, and skip landing-chamber
composition for samples outside the passage feature bound. No `assembler/world`
or mainline source was edited.

## Timings and remaining checks

The L80 comparison used one warm-up and five interleaved measured runs for each
binary, on all four owner-layer camera positions at W8 and W12 (96 runs total).
The window was Nov 4, 11:05–11:32 local; pre-run load was 0.42 and CPU idle was
99.4%. The stale prebuilt v240 binary failed its snapshot identity check, so the
baseline was rebuilt from committed L174 `0ff8d98` in
`Saved/Linux/l175/base-v240-src` (stamp `bf2d3bd4…`). Both versions use
`--seed=0` to build the same plan locally.

| Layer | Workers | LOD0–2 median v240 → v241 | Change | Whole-view median v240 → v241 | Change |
|---:|---:|---:|---:|---:|---:|
| 0 | 8 | 16.350 → 17.249 s | +5.50% | 17.361 → 18.241 s | +5.07% |
| 0 | 12 | 16.075 → 16.093 s | +0.11% | 17.037 → 17.046 s | +0.05% |
| 1 | 8 | 15.762 → 15.787 s | +0.16% | 16.676 → 16.645 s | −0.19% |
| 1 | 12 | 17.220 → 17.258 s | +0.22% | 18.048 → 18.083 s | +0.19% |
| 2 | 8 | 15.696 → 15.862 s | +1.06% | 16.517 → 16.655 s | +0.84% |
| 2 | 12 | 17.051 → 17.055 s | +0.03% | 17.803 → 17.802 s | −0.01% |
| 3 | 8 | 15.733 → 17.124 s | +8.84% | 16.549 → 17.959 s | +8.52% |
| 3 | 12 | 17.150 → 16.611 s | −3.15% | 17.949 → 17.402 s | −3.05% |

The timing result is inconclusive. A same-binary A/A control at layer 0/W8,
after one warm-up and 10 measured runs, ranged 15.560–17.747 s for LOD0–2
readiness and 16.619–18.844 s for whole-view readiness (Nov 4, 11:34–11:37).
That 13–14% same-binary spread is as large as or larger than the base/v241
median differences. The raw timing matrix and A/A logs are in
`Saved/Linux/l175/timing/`.

`verify.py fast` passed `streaming-admission-order-mid-pass-refill`, then
stopped on the expected first step-2 owner audit (`owner-floating-islands-style2-clang`).
That run reports one unsupported upper landing probe, 11 tube overlap pairs,
and one end-turn violation; source stamp, recipe, and style checks passed. The
canonical hash gate was not reached. Final-source Clang/GCC builds and hashes,
the 16-seed sweeps, injection control, and `git diff --check` ran. No Unreal
build or Windows compile was run.

Changed `Source/` files: **none**.